Field of the Invention
The present invention is related to a printed circuit board, and in particular to a printed circuit board manufactured by a non-plating process.
Description of the Related Art
The integrated circuit industry mainly comprises IC (Integrated Circuit) design, IC manufacturing, and chip test, wherein the current chip packaging technologies include Ball Grid Array (BGA), Chip-Size Package (CSP), Wafer Level Package (WLP), Three Dimension Package (3D package) and System in a Package (SIP). It is important for the stability of the IC that the chip structure directly affects the electric ability, mechanical ability, thermal ability, and the light sensitivity of the IC. Therefore, the chip structure has already become a core technique in the electronics industry.
At present, a chip mainly uses a printed circuit board as a substrate, and the chip would be disposed on the substrate, and the conducting pin of the chip is connected outward via the substrate. Multi Stacked-Die Packaging is arranged to integrate a plurality of dies into a single package to integrate multiple functions, save board space, reduce the space for dies, and lower the manufacturing cost. It should be noted that, generally, Multi Stacked-Die Packaging needs more than thousands of times of wiring the printed circuit board and dies. Therefore, the elements and chips of the printed circuit board fabricated by a non-plating process can easily become damaged during the wiring process of the Multi Stacked-Die Packaging due to electrostatic discharge (ESD).